A power semiconductor device is a semiconductor device used as a switch or rectifier in power electronics (e.g. switch-mode power supply). Such a device could be used in an integrated circuit, and the circuit becomes a Power IC, a High Voltage IC or a Smart Power circuit. A power semiconductor device is usually used in “commutation mode” (i.e. it is either on or off), and therefore has a design optimized for such usage.
High power devices used in integrated circuits typically operate with voltages in the range of 20V to 1.2 kV and current levels in the range of 1 mA to 50 A. Their application areas range from portable consumer electronics, domestic appliances, electric cars, motor control and power supplies to RF and microwave circuits and telecommunication systems.
Lateral power devices in integrated circuits (ICs) have the main terminals (anode/drain/collector as the high voltage terminal and cathode/source/emitter as the low voltage terminal) and the control terminal (gate/base) placed at the surface of the device in order to be easily accessible. In power ICs, such devices are often monolithically integrated with CMOS-type or BiCMOS-type low voltage/low power circuits. To minimize the cost, the high voltage power device and the low power CMOS circuits use common layers from the CMOS based process where possible. The drift layer is however specific to high voltage devices and it is commonly built before the CMOS process sequence.
Insulated gate bipolar transistors (IGBTs) belong to a very large group of high voltage power devices available in the market today. They have the combined advantage of a MOS gate drive and high current densities found in bipolar transistors. Electrical conductivity of the drift layer in an IGBT can be sharply increased due to conductivity modulation in the drift region. However, in general, a high level of charge leads to reduced on-state losses but increased switching losses.
Most IGBTs that are currently in the market are based on vertical designs. Vertical designs have the low voltage terminal, commonly called cathode or emitter, and the control terminal called gate, at the surface while the high voltage terminal called anode or collector at the bottom of the device. The vertical devices have high current capability, but they are not CMOS compatible. Lateral Insulated Gate Bipolar Transistors (LIGBTs) have been proposed as early as 1984 (M. Darwish, ‘Lateral Resurf COMFET’, Electronics Letters, vol. 20, no. 12, 1984), but in contrast to the vertical IGBTs, only a few SOI (Silicon On Insulator) and DI (Dielectric Isolation) solutions have been commercially successful.
The trade-off between the on-state voltage drop and turn-off losses is commonly adjusted in IGBTs by changing the lifetime of the charge carriers in the whole of the drift layer or locally at the drain. Lifetime killing in lateral power devices can be challenging since it can damage the CMOS or Bi-CMOS circuit blocks in an integrated circuit.
Another common approach used to adjust the trade-off between on-state and turn-off losses in IGBTs is based on changing the anode/drain/collector injection efficiency. This has been implemented by changing the doping of the semiconductor layers on either side of the injecting junction (e.g. drain P+ or n-type buffer). Changing the doping of the layers can be very difficult for lateral power devices, because most layers available in a CMOS or bi-CMOS process have doping concentrations dictated by the performance of the CMOS or Bi-CMOS low voltage devices. Moreover, even if some of these changes could be accommodated by introducing extra layers, it would be necessary to re-adjust the trade-off between on-state and switching losses in order for the device to operate more efficiently in a context of a particular application. The process therefore has to be re-tailored to allow this change, which can be expensive and time consuming.
US1991/US4989058 (Sel Colak et al.) reports a method of forming an LIGBT with improved switching performance. The anode/drain regions can be in direct contact with both P+ and N+ regions forming an anode shorted type LIGBT. The N+ region at the anode can be connected with the P+ region through a resistive element, thereby improving the LIGBT on-state. Alternatively a Schottky contact can be formed on the n-buffer instead of the Ohmic contact to anode P+, as a way to control the minority carrier injection and conductivity modulation.
A. Nakagawa et al. ‘500V Three Phase Inverter ICs Based on a New Dielectric Isolation Technique’, ISPSD 1992, pp 328-332 report an LIGBT having an anode structure characterized by an additional N+ region formed in a shallow P-drain layer. This reported structure behaves exactly in the same way as conventional anode shorted structure in the high injection condition. However in the low injection condition, the structure is the same as an ordinary LIGBT.
Terashima et al. ‘A Novel Driving Technology for a Passive Gate on a Lateral-IGBT’, ISPSD 2009, pp 45-48, investigate the LIGBT performance improvement by the use of a passive gate at the anode/drain side of the device. Passive gate can be driven without the need for additional process or structural change. The passive PMOS, whose gate is tied to a floating electrode, switches with the anode/drain voltage swing simultaneously. Therefore, low on resistance of a normal LIGBT and low turn-off loss of an anode shorted LIGBT can be achieved.
US2011/0057230A1 relates to a method of forming an LIGBT which has improved trade-off between on-state and turn-off losses while suppressing the parasitic thyristor latch-up. Drain/anode P+ doping can be reduced to lower the anode injection. A floating N+ region can be used in front of the drain/anode P+ to enhance the recombination. Alternatively N+ buried layer can be used under the drain/anode P+ to kill the injection of carriers deep into the substrate.
US2012/0061726A1 reports a method of forming an LIGBT having superior performance to the state-of-the-art. This superior performance is achieved by an anode structure consisting of a narrow P+-injector and a wide Schottky contact on a lightly doped P-layer over an n-buffer.
FIG. 1 shows schematically a cross-sectional view of a prior art LIGBT in bulk silicon technology. In this figure, an n-type region is formed in a p-type substrate 7 forming a drift region 3 which will be depleted of mobile carriers during the off-state blocking mode to support the breakdown voltage and conduct charge during the on-state conducting mode. A p-type region 1 forms an ohmic contact with a drain electrode. An n-type region 2 surrounds the p-type region 1 and is more highly doped than the drift region 3. The n-type region 2 prevents the punch through breakdown and can also be used to alter LIGBT characteristics. A p-well 4 forms a device channel region. A device gate electrode is placed on top of this region and is separated by a thin oxide. The gate electrode is used to control the charge in the channel region by controlling the flow of charge within the drift region 3. A further n-type region 5 and p-type region 6 are formed within the p-well 4 which are connected together forming the ohmic contact to the device source.
The LIGBT can be broadly regarded as a low voltage MOSFET, driving a wide based bipolar transistor. Depending on the technology there can be a second bipolar transistor which has a narrow base and a wide collector. FIG. 2 depicts the same LIGBT of FIG. 1 with the two bipolar transistors present in a LIGBT in bulk silicon technology. The vertical PNP transistor often allows injection of plasma deep into the p-substrate. The injection of plasma deep into the p-substrate will lead to slow switching speed and consecutively high switching losses. The switching speeds can be improved by reducing the gain of the PNP transistors. Furthermore by reducing the gain of the PNP transistors the parasitic thyristors in the LIGBT can be suppressed.
FIG. 3 and FIG. 4 depict prior art LIGBT designs proposed to lower the high switching losses present in LIGBTs. Many features of FIGS. 3 and 4 are similar to those shown in FIGS. 1 and 2 and therefore carry the same reference numerals. However, FIG. 3 shows an anode shorted type LIGBT where an N+ region 100 is connected to the drain electrode. This structure has improved switching performance but at the expense of higher conduction losses and snap-back characteristics in the on-state. The device structure on FIG. 4 has an N+ layer 110 in front of a drain P+ layer 1 and it is surrounded by a P-type layer 111. This device will operate without the snap-back type characteristics in the on-state and will have improved switching performance. However this design will require an additional masking layer to form the p-type layer 111.
The field of LIGBTs therefore continues to provide a need for an LIGBT having improved characteristics, for example increased switching speed and/or a wider range of operating conditions (e.g., any combination of one or more predetermined range of continuous and/or switching current between main terminals, voltage between main terminals, junction and/or ambient temperature, etc.).